Preliminary
ML696201 and ML69Q6203
Pin Configuration
21
NC
20
NC
19
NC
18
EFIQ_N
17
NC
16
NC
15
PIOD[0]/
SCLD
14
PIOD[1]/
WSD
13
PIOD[3]/
CKOUTD
12
PIOD[6]/
SDA
11
PIOD[8]/
SSIOTXD
[0]
VDD_FLA
10
PIOD[11]/
SSIOTXD
[1]
PIOD[9]/
SSIORXD
[0]
PIOD[10]/
SSIOCK[0]
9
PIOD[12]/
SSIORXD
[1]
PIOD[13]
SSIOCK[1]
8
PIOD[14]/
UP_TXD
7
PWMOUT
6
TMODE[2]
5
TMODE[0]
4
BOOT[1]
3
GND_
CORE
2
GND_IO
1
GND_IO
AA
NC
NC
NC
NC
GND_IO
NC
GND_IO
VDD_
CORE
PIOD[2]/
SDD
PIOD[4]/
SCLA/SCL
SCL
TEST_
RSV
TMODE[1]
EXTBUS
BOOT[0]
GND_
CORE
GND_IO
TDO
Y
NC
NC
NC
NC
GND_IO
RESET_N
GND_IO
VDD_
CORE
VDD_
CORE
PIOD[5]/
WSA
PIOD[7]/
CKOUTA/
CKOUT
GND_
CORE
PIOD[15]/
UP_RXD
SDAT
PLL
BYPASS
TMODE[3]
IDEMODE
GND_
CORE
GND_IO
FD[0]/
IDED[0]
VSSFLA
W
NC
NC
NC
NC
GND_IO
GND_IO
GND_IO
VDD_
CORE
VDD_IO
VDD_IO
GND_
CORE
VDD_IO
VDD_IO
VDD_
CORE
VDD_IO
VDD_IO
GND_IO
nTRST
FD[2]/
IDED[2]
FD[1]/
IDED[1]
V
NC
NC
ADIN[1]
AVDD
GND_IO
RTCK
FD[6]/
IDED[6]
FD[4]/
IDED[4]
U
NC
ADIN[2]
ADIN[3]
GND_
CORE
VDD_IO
TCK
PIOF[0]/
IDED[8]
FD[7]/
IDED[7]
T
ADIN[0]
AGND
VSSFLA
VDD_IO
VDD_IO
TMS
PIOF[3]/
IDED[11]
PIOF[2]/
IDED[10]
R
VDD_PLL
OSC48M0 OSC48M1B
VDD_
CORE
VDD_
CORE
TDI
PIOF[5]/
IDED[13]
PIOF[4]/
IDED[12]
P
USB_
VOREF
USB_
ATEST[0]
VDD_PLL
OSC11M0
VDD_
CORE
FD3/
IDED[3]
IDED[15]
PIOF[6]/
IDED[14]
N
USB_
REXT
AVDDC
GND_PLL OSC11M1B
GND_
CORE
FD[5]/
IDED[5]
OSC32K1B
GNDRTC
M
AVDDRX
AGNDC
USB_
ATEST[1]
GND_PLL
272-Pin LFBGA
(TOP VIEW)
VDD_IO
PIOF[1]/
IDED[9]
RTC_
TESTMODE
OSC32K
[0]
L
USB_DP
AGNDTX
DREQCLR
TCOUT
VDD_IO
32K_
IDE
TESTMODE NPCBRID
IDEIRQ
K
USB_DM
AGNDTX
XDQM[0]
DREQ
VDD_IO
VDDRTC
IDEDACK
_N
IDEREQQ
J
AVDDTX
AGNDRX
XSDCKE
XDQM[1]
VDD_IO
FCLE/
IDECS_N
[0]
IDERST_
N
FRB/
IDERDY
FALE/
IDECS_N
[1]
FWR_N/
IDEWR_N
H
XCAS_N
XRAS_N
VDD_IO
XSYSCLK
VDD_
CORE
FRD_N/
IDERE_N
G
PIOC[1]/
XWAIT
[1]
PIOC[2]/
XBS_N
[0]
GND_IO
XSDCS_N
PIOC[0]/
XWAIT
[0]
PIOC[3]/
XBS_N
[1]
VDD_IO
XSDCLK
VDD_
CORE
IDEA[1]
IDEA[2]
IDEA[0]
F
PIOC[4]/
XIOCS_N
[0]
GND_IO
VDD_IO
GND_
CORE
GND_
CORE
PIOE[1]
PIOE[0]
E
GND_IO
GND_
CORE
PIOC[5]/
XIOCS_N
[1]
PIOB[7]/
XD[7]
GND_
CORE
GND_
CORE
VDD_IO
VDD_IO
VDD_IO
VDD_
CORE
GND_
CORE
VDD_IO
VDD_IO
VDD_
CORE
VDD_
CORE
GND_IO
GND_IO
PIOE[5]
PIOE[3]
PIOE[2]
D
PIOC[9]/
XROMCS
_N
PIOC[11]/
XOE_N
PIOC[10]/
XWE_N
GND_IO
PIOC[6]/
XIOCS_N
[10]
PIOB[2]/
XD[2]
PIOC[7]/
PIOC[8]/
XIOCS_N XRAMCS_N
[11]
PIOB[10]/
XD[10]
PIOB[12]/
XD[12]
PIOB[5]/
XD[5]
PIOB[9]/
XD[9]
PIOB[13]/
XD[13]
PIOA[3]/
XA[4]
PIOA[7]/
XA[8]
PIOA[10]/
XA[11]
PIOC[12]/
XA[17]
XA[21]
PIOE[15]
PIOE[6]
PIOE[4]
GND_IO
PIOE[8]
PIOE[7]
C
GND_IO
PIOB[0]/
XD[0]
PIOA[0]/
XA[1]
PIOB[15]/
XD[15]
PIOA[1]/
XA[2]
PIOA[5]/
XA[6]
PIOA[9]/
XA[10]
PIOA[12]/
XA[13]
PIOA[15]/
XA[16]
PIOC[14]/
XA[19]
XA[23]
PIOE[12]
PIOE[13]
PIOE[10]
GND_IO
PIOE[9]
B
GND_IO
PIOB[1]/
XD[1]
PIOB[3]/
XD[3]
PIOB[4]/
XD[4]
PIOB[6]/
XD[6]
PIOB[8]/
XD[8]
PIOB[11]/
XD[11]
PIOB[14]/
XD[14]
PIOA[2]/
XA[3]
PIOA[4]/
XA[5]
PIOA[6]/
XA[7]
PIOA[8]/
XA[9]
PIOA[11]/
XA[12]
PIOA[13]/
XA[14]
PIOA[14]/
XA[15]
PIOC[13]/
XA[18]
PIOC[15]/
XA[20]
XA[22]
PIOE[14]
PIOE[11]
GND_IO
A
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 1. 272-Pin LFBGA
Notes:
1. For pins that have multiple functions, the signals are noted by their pri-
mary / secondary functions.
2. NC pins can be connected to VDD_IO or GND.
Oki Semiconductor • 5
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