ML675001/ML67Q5002/ML67Q5003
Pin Descriptions
Primary/
Pin Name
I/O
Description
Secondary
Logic
System
RESET_N
BSEL[1:0]
I
I
Reset input
–
–
Negative
Positive
Boot device select signal.
BSEL[1]
BSEL[0]
Boot device
L
L
L
H
*
Internal Flash (External ROM for ML675001)
External ROM
H
Boot ROM (* = don’t care)
The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF) after reset.
Clock mode inputs. Normally connected to GND.
CLKMD[1:0]
OSC0
I
I
–
–
Positive
–
Crystal oscillator connection or external clock input.
If used, connect a crystal oscillator (5 MHz to 14 MHz) to OSC0 and OSC1_N.
It is also possible to input a direct clock (5 MHz, 20 MHz to 56 MHz).
OSC1_N
O
Oscillation output pin.
–
–
When not using a crystal oscillator, leave this pin unconnected.
CKO
O
I
Clock out.
–
–
–
CKOE_N
Clock out enable.
Negative
JTAG Interface
TCK
I
I
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally leave open.
–
–
–
–
–
–
TMS
Positive
Negative
Positive
Positive
nTRST
I
TDI
I
TDO
O
General-purpose I/O Interface
PIOA[7:0]
I/O
I/O
I/O
I/O
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Primary
Primary
Primary
Primary
Positive
Positive
Positive
Positive
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
General-purpose port.
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Note that enabling the DRAM controller by asserting the DRAME_N inputs permanently con-
figures PIOD[7:0] for their secondary functions, making them unavailable for use as port
pins.
PIOE[9:0]
I/O
O
General-purpose port. Not available for use as port pins when secondary functions are in
use.
Primary
Positive
Positive
External Bus Interface (Global)
XA[23:19]
Address bus to external RAM, external ROM, external I/O banks, and external DRAM.After
a reset, these pins are configured for their primary function PIOC[6:2].
Secondary
XA[18:0]
XD[15:0]
O
Address bus to external RAM, external ROM, external I/O banks, and external DRAM.
Data bus to external RAM, external ROM, external I/O banks, and external DRAM.
–
–
Positive
Positive
I/O
External Bus Interface (ROM, SRAM and I/O)
XROMCS_N
XRAMCS_N
XIOCS_N[0]
XIOCS_N[1]
XIOCS_N[2]
O
O
O
O
O
ROM bank chip select.
SRAM bank chip select.
I/O chip select 0.
–
–
–
–
–
Negative
Negative
Negative
Negative
Negative
I/O chip select 1.
I/O chip select 2.
12 • Oki Semiconductor
April 2004, Rev 2.0
OKI [ OKI ELECTRONIC COMPONETS ]
