欢迎访问ic37.com |
会员登录 免费注册
发布采购

ML674000TB 参数 Datasheet PDF下载

ML674000TB图片预览
型号: ML674000TB
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 32-Bit, 33.333MHz, CMOS, PQFP128, 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-128]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 28 页 / 189 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
 浏览型号ML674000TB的Datasheet PDF文件第6页浏览型号ML674000TB的Datasheet PDF文件第7页浏览型号ML674000TB的Datasheet PDF文件第8页浏览型号ML674000TB的Datasheet PDF文件第9页浏览型号ML674000TB的Datasheet PDF文件第11页浏览型号ML674000TB的Datasheet PDF文件第12页浏览型号ML674000TB的Datasheet PDF文件第13页浏览型号ML674000TB的Datasheet PDF文件第14页  
ML674000  
Oki Semiconductor  
Pin Number  
LFBG  
Primary Function  
Function  
Secondary Function  
Pin Name I/O Function  
TQFP  
Pin Name I/O  
A
GN  
D
76  
H12  
GND_IO  
I/O ground  
77  
78  
79  
80  
81  
H10  
H11  
G12  
G10  
G11  
VDD_IO VDD I/O power supply  
XA[9]  
XA[10]  
XA[11]  
XA[12]  
O
O
O
O
External address output  
External address output  
External address output  
External address output  
GN  
D
82  
G13 GND_CORE  
Core ground  
83  
84  
85  
86  
87  
88  
F11 VDD_CORE VDD Core power supply  
F10  
F12  
E12  
F13  
E10  
XA[13]  
XA[14]  
XA[15]  
XA[16]  
XA[17]  
O
O
O
O
O
External address output  
External address output  
External address output  
External address output  
External address output  
GN  
D
89  
90  
91  
D12  
E13  
E11  
GND_IO  
XA[18]  
I/O ground  
O
O
External address output  
General-purpose port (with interrupt  
function)  
PIOA[10]  
I/O  
XA[19]  
External address output  
General-purpose port (with interrupt  
function)  
92  
D11  
PIOA[11]  
PIOA[12]  
I/O  
I/O  
XA[20]  
O
External address output  
External address output  
General-purpose port (with interrupt  
function)  
93  
94  
95  
D13  
C12  
D10  
XA[21]  
O
O
VDD_IO VDD I/O power supply  
General-purpose port (with interrupt  
function)  
PIOA[13]  
PIOA[14]  
PIOA[15]  
I/O  
I/O  
I/O  
XA[22]  
External address output  
External address output  
General-purpose port (with interrupt  
function)  
96  
97  
B12  
A12  
XA[23]  
XWR  
O
O
General-purpose port (with interrupt  
function)  
External bus data transfer  
direction  
98  
99  
A11  
C10  
XOE_N  
XWE_N  
O
O
Output enable (except SDRAM)  
Write enable  
GN  
D
100 B11  
GND_IO  
I/O ground  
101 A10 XBWE_N[0]  
102 C9 XBWE_N[1]  
103 B10 XROMCS_N  
O
O
O
O
O
O
Write enable (LSB)  
Write enable (MSB)  
External ROM chip select  
External RAM chip select  
I/O bank 0 chip select  
I/O bank 1 chip select  
104  
105  
106  
A9 XRAMCS_N  
D9 XIOCS_N[0]  
B9 XIOCS_N[1]  
GN  
D
107  
108  
109  
A8 GND_CORE  
Core ground  
I
B8 VDD_CORE VDD Core power supply  
General-purpose port (with interrupt  
function)  
D8  
PIOB[0]  
PIOB[1]  
I/O  
I/O  
DREQ0  
DMA request signal (Ch 0)  
DREQ clear signal (Ch 0)  
General-purpose port (with interrupt  
function)  
110  
111  
C8  
B7  
DREQCLR0  
O
VDD_IO VDD I/O power supply  
8/22