FEDL63193-04
Semiconductor
1
ML63193
BLOCK DIAGRAM
Asterisks (*) indicate the secondary function of each port. Signal names enclosed by chain lines (
Indicate interface signals of the V
DDI
power supply system.
)
CPU core nX-4/250
TIMING
CON-
TROL
SP
RSP
STACK
CAL.S:16-level
REG.S:16-level
ALU
MIE
INSTRUCTION
DECODER
IR
INT
4
RAM
2048N
INT
2
SIO
INT193
INT
1
SFT
RESET
TST1
TST2
RST
INT
DATA BUS
TST
4
TBC
MULDIV
INT
1
MELODY
CBR
EBR
H
X
L
Y
C
RA
A
G
Z
BUS
CON-
TROL
PC
ROM
64KW
TIMER
8bit (4ch)
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
RXC*
TXC*
RXD*
TXD*
SCLK*
SIN*
SOUT*
MD
MDB
XT0
XT1
OSC0
OSC1
V
DDH
V
DD
CB1
CB2
V
DD1
V
DD2
V
DD3
V
DD4
V
DD5
C1
C2
V
DDL
OSC
INT
1
INT
1
BACK
UP
BLD
INT
1
INPUT
PORT
P0.0 - P0.3
100HzTC
P9.0 - P9.3
WDT
INT
3
PA.0 - PA.3
I/O
PORT
PB.0 - PB.3
PC.0 - PC.3
PE.0 - PE.3
BIAS
LCD
&
DSPR
COM1 - 16
SEG0 - 63
V
DDI
V
SS
5/37
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