FEDL63187B-06
1Semiconductor
ML63187B/63189B
PAD CONFIGURATION (ML63187B)
Pad Layout
56 COM12
VDDI 83
55 COM11
54 COM10
53 COM9
52 SEG63
51 SEG62
50 SEG61
49 SEG60
48 SEG59
47 SEG58
46 SEG57
45 SEG56
44 SEG55
43 SEG54
42 SEG53
41 SEG52
40 SEG51
39 SEG50
38 SEG49
37 SEG48
36 SEG47
35 SEG46
34 SEG45
33 SEG44
32 SEG43
31 SEG42
30 SEG41
29 SEG40
28 SEG39
27 SEG38
PE.0 84
PE.1 85
PE.2 86
PE.3 87
PB.0 88
PB.1 89
PB.2 90
PB.3 91
COM1 92
COM2 93
COM3 94
COM4 95
COM5 96
COM6 97
COM7 98
COM8 99
SEG0 100
SEG1 101
SEG2 102
SEG3 103
SEG4 104
SEG5 105
SEG6 106
SEG7 107
SEG8 108
SEG9 109
SEG10 110
SEG11 111
Y
X
(0,0)
Chip size
: 4.238 mm × 4.914 mm
Chip thickness
Coordinate origin
Pad hole size
Pad size
: 350 µm (280 µm: available as required)
: center of chip
: 100 µm × 100 µm
: 110 µm × 110 µm
Minimum pad pitch : 140 µm
Note: The chip substrate voltage is VSS.
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