FEDL63187B-06
1Semiconductor
ML63187B/63189B
BLOCK DIAGRAM (ML63187B)
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied to the circuits
corresponding to the signal names inside
from VDDI (power supply for interface).
CPU CORE
nX-4/250
H
X
L
CBR
RA
PC
TIMING
CON-
TROL
ROM
16 KW
Y
EBR
A
C
G
Z
SP
BUS
ALU
CON-
TROL
RSP
MIE
IR
INSTRUCTION
DECODER
STACK
CAL : 16-level
REG : 16-level
INT
4
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
TIMER
8 bit × 4
RAM
1024N
T13CK*
RESET
RST
INT187
INT
1
INT
4
SCLK*
SIN*
TST1
TST2
TST
TBC
BLD
SFT
SOUT*
XT0
XT1
INT
1
INT
1
OSC
OSC0
OSC1
100 HzTC
WDT
MD
MELODY
MDB
INT
1
VDDH
VDD
PB.0-PB.3
PE.0-PE.3
BACK
UP
I/O
PORT
INT
2
CB1
CB2
VDD1
VDD2
VDD3
VDD4
VDD5
C1
BIAS
LCD
&
DSPR
COM1-16
SEG0-63
VDD1
VSS
C2
VDDL
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