FEDL63187B-06
1Semiconductor
ML63187B/63189B
Table 2 shows the secondary functions of each pin of the ML63187B, ML63189B.
Table 2 Pin Descriptions (Secondary Functions)
Pin No.
Pad No.
Function
Symbol
Type
Description
ML63187B ML63189B ML63187B ML63189B
External 0 interrupt input pins
The change of input signal level causes an
interrupt to occur.
PB.0/INT0
PB.1/INT0
PB.2/INT0
PB.3/INT0
75
76
77
78
74
75
76
77
88
89
90
91
98
99
I
The Port B Interrupt Enable register
(PBIE) enables or disables an interrupt for
each bit.
100
101
External 2 interrupt input pin
The change of input signal level causes an
interrupt to occur.
External
Interrupt
PE.3/INT2
74
73
87
97
I
I
External 5 interrupt input pins
P0.0/INT5
P0.1/INT5
86
87
88
89
74
110
111
112
113
98
The change of input signal level causes an
interrupt to occur.
—
—
The Port 0 Interrupt Enable register (P0IE)
enable or disable an interrupt for each bit.
Applied to the ML63189B only.
P0.2/INT5
P0.3/INT5
PB.0/TM0CAP
75
76
75
76
88
89
88
89
I
Timer 0 capture input pin
Capture
Timer
PB.1/TM1CAP
PB.0/TM0OVF
PB.1/TM1OVF
75
74
75
99
98
99
I
Timer 1 capture input pin
O
O
Timer 0 overflow flag output pin
Timer 1 overflow flag output pin
External clock input pin for timer 0 and
timer 2
PB.2/T02CK
PB.3/T13CK
77
78
76
77
90
91
100
101
I
I
External clock input pin for timer 1 and
timer 3
Shift register receive data input pin
PE.0/SIN
71
72
70
71
84
85
94
95
I
Shift register transmit data output pin
Shift register clock input-output pin
PE.1/SOUT
O
Shift
Register
PE.2/SCLK
73
72
86
96
I/O Clock output when this device is used as a
master processor.
17/36
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