FEDL63187B-06
1Semiconductor
ML63187B/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Pin No.
Pad No.
Function
Test
Symbol
Type
Description
Input pins for testing
A pull-down resistor is internally connected to
these pins.
ML63187B ML63189B ML63187B ML63189B
TST1
TST2
61
62
63
64
79
80
89
90
I
I
The user cannot use these pins.
Reset input pin
Setting this pin to “H” Ievel puts this device
into a reset state.
Then, setting this pin to “L” Ievel starts
executing an instruction from address 0000H.
A pull-down resistor is internally connected to
this pin.
RESET
58
60
76
86
I
Reset
An option of using RESET sampling circuit or
not is chosen by the mask option.
When using RESET sampling circuit, the
system reset mode is entered by holding the
RESET pin at a “H” Ievel for 1 ms or more.
Melody output pin (non-inverted output)
Melody output pin (inverted output)
MD
MDB
63
64
66
67
86
81
82
91
92
O
O
Melody
4-bit input ports
P0.0/INT5
110
Pull-up resistor input, pull-down resistor input,
or high-impedance input is selectable for
each bit.
P0.1/INT5
P0.2/INT5
P0.3/INT5
87
88
89
111
112
113
—
—
I
Applied to the ML63189B only.
P9.0
P9.1
P9.2
82
83
84
106
107
108
4-bit input-output ports
In input mode, pull-up resistor input, pull-
down resistor input, or high-impedance input
is selectable for each bit.
—
—
—
—
I/O
I/O
P9.3
PA.0
PA.1
PA.2
PA.3
85
78
79
80
81
109
102
103
104
105
In output mode, P-channel open drain output,
N-channel open drain output, CMOS output,
or high-impedance output is selectable for
each bit.
P9.0 to P9.3 and PA.0 to PA.3 are applied to
the ML63189B only.
Port
PB.0/INT0/
TM0CAP/
TM0OVF
PB.1/INT0/
TM1CAP/
TM1OVF
PB.2/INT0/
T02CK
75
76
74
75
88
89
98
99
I/O
I/O
77
78
76
77
90
91
100
101
PB.3/INT0/
T13CK
PE.0/SIN
PE.1/SOUT
PE.2/SCLK
PE.3/INT2
71
72
73
74
70
71
72
73
84
85
86
87
94
95
96
97
14/36
OKI [ OKI ELECTRONIC COMPONETS ]
