¡ Semiconductor
Endpoint 0 Receive Byte Count Register (C9h, –)
D7
RFU
D6
D5
D4
D3
EP0 Byte Count (R)
D2
D1
D0
ML60851A
Endpoint 1 Receive Byte Count Register (CAh, –)
D7
RFU
D6
D5
D4
D3
EP1 Byte Count (R)
D2
D1
D0
Endpoint 2 Receive Byte Count Register (CBh, –)
D7
RFU
D6
D5
D4
D3
EP2 Byte Count (R)
D2
D1
D0
Flash Transmit FIFO (–, 4Eh)
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
In case EP1 is set as a transmission endpoint, when "1" is
written in this bit, the FIFO at EP1 is cleared and Packet
Ready at EP1 is reset by the WRITE pulse.
In case EP2 is set as a transmission endpoint, when "1" is
written in this bit, the FIFO at EP2 is cleared and Packet
Ready at EP2 is reset by the WRITE pulse.
In case EP3 is set as a transmission endpoint, when "1" is
written in this bit, the FIFO at EP3 is cleared and Packet
Ready at EP3 is reset by the WRITE pulse.
Note: Please clear all FIFOs at the same time, otherwise some of them may not be cleared.
System Control (–, 4Fh)
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
When "1" is written in this bit, the ML60851A is reset
by the WRITE pulse.
Oscillation Stop Command
Oscillation Stop Command: Writing 1010b to D7 to D4, (writing A0h into this register) causes the
oscillator circuit of the ML60851A to be deactivated and go into the standby mode.
When oscillation is stopped, reading and writing into the register is possible but reading and writing
into FIFO is not possible. Asserting the
RESET
pin restarts oscillation.
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OKI [ OKI ELECTRONIC COMPONETS ]
