¡ Semiconductor
ML60851A
Interrupt Status Register (DCh, 5Ch) (R)
D7
D6
D5
D4
D3
D2
D1
D0
Setup Ready
Interrupt Status (R)
EP1 Packet Ready
Interrupt Status (R)
EP2 Packet Ready
Interrupt Status (R)
EP0 Receive Packet Ready
Interrupt Status (R)
EP0 Transmit Packet Ready
Interrupt Status (R)
USB Bus Reset
Interrupt Status
Suspended State
Interrupt Status (R)
EP3 Packet Ready
Interrupt Status
SetupReadyInterruptStatus: EquivalenttoSetupReadyat(F3h)describedlaterwhenthecorresponding
Interrupt Enable bit is asserted.
EP1PacketReadyInterruptStatus: EquivalenttoEP1ReceivePacketReady(thecomplementofEP1
Transmit Packet Ready when EP1 is set for transmitter) at (C8h) described before when the
corresponding Interrupt Enable bit is asserted.
EP2PacketReadyInterruptStatus: EquivalenttoEP2ReceivePacketReady(thecomplementofEP2
Transmit Packet Ready when EP2 is set for transmitter) at (C8h) described before when the
corresponding Interrupt Enable bit is asserted.
EP0ReceivePacketReadyInterruptStatus: EquivalenttoEP0ReceivePacket Ready at (C8h) described
before when the corresponding Interrupt Enable bit is asserted.
EP0TransmitPacketReadyInterruptStatus: EquivalenttothecomplementofEP0TransmitPacket
Ready at (C8h) described before when the corresponding Interrupt Enable bit is asserted.
USB Bus Reset Interrupt Status: This bit is set to "1" at USB bus reset when the D5 bit of the interrupt
enable register (DBh) is "1". To return this bit back to "0", "1" should be written to the D5 bit of the
device states register.
SuspendedStateInterruptStatus: EquivalenttoSuspendedStateRegisterat(C1h)describedbefore
when the corresponding Interrupt Enable bit is asserted.
EP3 Packet Ready Interrupt Status: When the D7 bit of the interrupt enable register (DBh) is "1", the
complement of the D7 bit of the endpoint packet ready register (C8h) is being copied.
12/44
OKI [ OKI ELECTRONIC COMPONETS ]
