PEDL60851C-02
1
Semiconductor
ML60851C
End Point 0 Receive Byte Count Register (EP0RXCNT)
Read address
Write address
C9h
—
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
0
0
0
0
Byte count of EP0 (R)
The ML60851C automatically counts the number of bytes in the packet being received by EP0 and stored it in this
register. Although the counting is performed up to the maximum packet size entered in the payload register in the
case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to
this value and reads the data of one packet from the EP0RXFIFO.
The EP0 receive byte count register is cleared under the following conditions:
1. When the local MCU resets the EP0 receive packet ready bit (by writing a “1” in PKTRDY(0)).
2. When a setup packet is received.
3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).
End Point 1 Receive Byte Count Register (EP1RXCNT)
Read address
Write address
CAh
—
D7
0
D6
0
D5
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
0
0
0
0
0
Byte count of EP1 (R)
The ML60851C automatically counts the number of bytes in the packet being received by EP1 and stored it in this
register. Although the counting is performed up to the maximum packet size entered in the payload register in the
case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to
this value and reads the data of one packet from the EP1 receive FIFO.
This register is invalid when the EP1 transfer direction is set as ‘Transmit’.
The EP1 receive byte count register is cleared under the following conditions:
1. When an OUT token is received for EP1.
2. When the EP1 receive packet ready bit is reset (by writing a “1” in PKTRDY(1)).
3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).
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