PEDL60851C-02
1
Semiconductor
ML60851C
End Point 0 Transmit FIFO (EP0TXFIFO)
Read address
Write address
D7
After a hardware reset
After a bus reset
Definition
x
x
D6
x
x
—
C0h
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
EP0 Transmit data (W)
The EP0 transmit data can be written in by writing to the address C0h. The receive data from the host in the data
stage during a control read transfer is stored in EP0TXFIFO. When the ML60851C issues an EP0 transmit packet
ready interrupt request, the local MCU writes the transmit data to the address C0h. It is possible to write the packet
data successively by writing continuously.
The EP0 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP0.
2. When a setup packet is received.
End Point 1 Transmit FIFO (EP1TXFIFO)
Read address
Write address
D7
After a hardware reset
After a bus reset
Definition
x
x
D6
x
x
—
C1h
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
EP1 Transmit data (W)
The EP1 transmit data can be written in by writing to the address C1h. When EP1 has been set for bulk
transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851C
issues an EP1 packet ready interrupt request. It is possible to write the packet data successively by writing
continuously. When the data transfer direction of EP1 is set as ‘Receive’, all accesses to this address will be
invalid.
The EP1 transmit FIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP1.
2. When the local MCU writes a “1” in the EP1FIFO clear bit (CLRFIFO(1)).
Even when a DMA write with a 16-bit width is made in EP1TXFIFO, the address is A7:A0 = 41h.
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