PEDL60851C-02
ML60851C
¡ Semiconductor
• Interrupt
Interrupt factors include Packet Ready for a transmit/receive FIFO, Setup Ready for 8-byte setup
data, and Suspend. Generation of each interrupt request can be enabled or disabled by the
Interrupt Enable register.
• DMA
8-bitand16-bitdemandtransferDMAandsingletransferDMAareenabledforbulk-transferFIFO
at endpoint address 1.
In Demand Transfer mode, DREQ is asserted when a valid packet arrives at the FIFO. When the
external DMA contoller has completed transferring all byte data of a received packet, DREQ is
deasserted. Accordingly, other devices cannot access the local bus during DMA transfer.
In Single Tranfer mode, each time transfer of one byte data is completed, DREQ is deasserted.
While DREQ is deasserted, other devices can access the local bus.
• Remote Wakeup
This functional block supports the remote wakeup function.
• USB Transfers
The ML60851C supports the two transfer types (Control Transfer and Bulk Transfer) of four
transfer types (Control, Isochronous, Interrupt, and Bulk) defined by the USB Specifications.
- TheControlTransferisrequiredfortransferofconfiguration,commands,andstatusinformation
between the host and devices.
- TheBulkTransferenablestransferofalargeamountofdatawhenthebusbandwidthisenough.
• USB Transceiver
The ML60851C contains an Oki's USB transceiver which converts internal unidirectional signals
into USB-compatible signals.
This enables the designer's application module to interface to the physical layer of the USB.
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OKI [ OKI ELECTRONIC COMPONETS ]
