PEDL60851C-02
ML60851C
¡ Semiconductor
• FIFO Control
The FIFO Control block controls all FIFO operations for transmitting and receiving USB packets.
The FIFO configuration is described below.
Endpoint FIFO/8-Byte Setup Register Configuration
For Control Transfer
8-Byte
Endpoint Address 0
Endpoint Address 0
Setup Register
Setup Ready
8-Byte
EP0 Receive FIFO
EP0 Transmit FIFO
FIFO Rx
Packet Ready
8-Byte
Endpoint Address 0
FIFO Tx
Packet Ready
For Bulk Transfer
64-Byte
FIFO
Packet Ready
DMA Request
EP1 FIFO (128 bytes)
(Selectable for transmitter
or receiver)
64-Byte
FIFO
Endpoint Address 1
Endpoint Address 2
EP2 FIFO (64 bytes)
(Selectable for transmitter
or receiver)
64-Byte
FIFO
Packet Ready
8-Byte
FIFO
Endpoint Address 3
EP3 FIFO (8 bytes)
Packet Ready
FIFO type
Reception
Endpoint address
Program size
Function
0
0
1
2
3
8 Bytes
Transfer control
Transfer control
Bulk-In and bulk-Out
Bulk-Out and bulk-In
Interrupt
Transmission
8 Bytes
Reception/Transmission
Reception/Transmission
Transmission
64 Bytes (2 levels)
64 Bytes
8 Bytes
Every FIFO has a flag that indicates a full or empty FIFO and the capability of re-transmitting and
re-receiving data. Endpoint addresses 1 and 2 can be used for either of reception and transmission
by writing the register.
The FIFO at endpoint address 1 can be used for DMA transfer.
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