ML2612 FAMILY DATASHEET
HVDD 3 or 2 wire serial interface clock IO. If this pin is (input)
17
C5
B3
S3_SCLK
/S2_SCLK
I
-
used with external pull-up resistor, it possibly gets
noise from power. Therefore tamper noise design is
required in the noisy environment.
11
15
S3_CSB
/MCLKO
IO HVDD When IFSEL=L, chip select input for 3 wire serial (input)/L -/ Open
interface. When IFSEL=H,256fs clock output.
N/A RESETB
I
HVDD Active-low reset input.
Apply for ML2612GD
(input)
-
Version: 3
11