FEDL2250DIGEST-09
OKI Semiconductor
ML2250 family
To read the channel status, input “L” level to ÝÍ and ÎÜ pins. DQ pin will output the channel status in
synchronization with SCK clock.
The selection of rising/falling edge of SCK clock, similar to when inputting the commands and data, is determined
by the level at SCK pin at the falling edge of ÎÜ pin.
The status signals in the parallel interface are output to D7 to D0 pins sequentially from D7.
Status Read Timing
SCK Rising Edge Operation
CS(I)
RD(I)
SCK(I)
Hi-Z
Hi-Z
DO(O)
D7 D6 D5 D4 D3 D2 D1 D0
SCK Falling Edge Operation
CS(I)
RD(I)
SCK(I)
Hi-Z
Hi-Z
DO(O)
D7 D6 D5 D4 D3 D2 D1 D0
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