¡ Semiconductor
MSM81C55-5RS/GS/JS
Basic Input Mode
tRP
RD
tPR
Port Input
Data Bus
Basic Output Mode
WR
tWP
Data Bus
Port Output
Note: The DATA BUS timing is the same as the read and write cycles.
Timer Waveforms 1
Load Counter From
Count Length Register
Load Counter From
Count Length Register
2
1
5
4
3
2
1
5
tf
t2
(T.C)
TIMER IN
t
1
tr
tCYC
TIMER OUT
(Note)
(Pulse)
tTL
tTH
TIMER OUT
(Square Wave)
(Note)
tTL
tTH
Count Down(5Æ1)
Note: Periodically outut according to the output mode (m1=1) programming contents.
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