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PCF8591P 参数 Datasheet PDF下载

PCF8591P图片预览
型号: PCF8591P
PDF下载: 下载PDF文件 查看货源
内容描述: 8位A / D和D / A转换器 [8-bit A/D and D/A converter]
分类和应用: 转换器模拟IC信号电路光电二极管
文件页数/大小: 28 页 / 140 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
Product specification
8-bit A/D and D/A converter
PCF8591
handbook, halfpage
msb
lsb
0
0
1
A2
A1
A0
R/W
1
fixed part
handbook, halfpage
programmable part
MBL824
AIN0
AIN1
AIN2
AIN3
A0
A1
A2
VSS
1
2
3
4
16 VDD
15 AOUT
14 VREF
13 AGND
Fig.4 Address byte.
PCF8591T
5
6
7
8
MBL823
12 EXT
11 OSC
10 SCL
9 SDA
7.2
Control byte
The second byte sent to a PCF8591 device will be stored
in its control register and is required to control the device
function. The upper nibble of the control register is used for
enabling the analog output, and for programming the
analog inputs as single-ended or differential inputs. The
lower nibble selects one of the analog input channels
defined by the upper nibble (see Fig.5). If the
auto-increment flag is set, the channel number is
incremented automatically after each A/D conversion.
If the auto-increment mode is desired in applications
where the internal oscillator is used, the analog output
enable flag in the control byte (bit 6) should be set. This
allows the internal oscillator to run continuously, thereby
preventing conversion errors resulting from oscillator
start-up delay. The analog output enable flag may be reset
at other times to reduce quiescent power consumption.
The selection of a non-existing input channel results in the
highest available channel number being allocated.
Therefore, if the auto-increment flag is set, the next
selected channel will be always channel 0. The most
significant bits of both nibbles are reserved for future
functions and have to be set to logic 0. After a Power-on
reset condition all bits of the control register are reset to
logic 0. The D/A converter and the oscillator are disabled
for power saving. The analog output is switched to a
high-impedance state.
Fig.3 Pinning diagram (SO16).
7
7.1
FUNCTIONAL DESCRIPTION
Addressing
Each PCF8591 device in an I
2
C-bus system is activated by
sending a valid address to the device. The address
consists of a fixed part and a programmable part. The
programmable part must be set according to the address
pins A0, A1 and A2. The address always has to be sent as
the first byte after the start condition in the I
2
C-bus
protocol. The last bit of the address byte is the
read/write-bit which sets the direction of the following data
transfer (see Figs 4, 16 and 17).
2003 Jan 27
5