PCF8563
NXP Semiconductors
Real-time clock/calendar
8.3.2.1 Interrupt output
Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a
timer countdown, TF is set to logic 1. These bits maintain their value until overwritten
using the interface. If both timer and alarm interrupts are required in the application, the
source of the interrupt can be determined by reading these bits. To prevent one flag being
overwritten while clearing another, a logic AND is performed during a write access.
TI_TP
TE
e.g. AIE
to interface:
read TF
TF: TIMER
SET
TIE
0
1
COUNTDOWN COUNTER
0
1
PULSE
GENERATOR 2
CLEAR
TRIGGER
CLEAR
INT
from interface:
clear TF
AIE
to interface:
read AF
AF: ALARM
FLAG
set alarm
flag AF
SET
CLEAR
from interface:
clear AF
013aaa087
When bits TIE and AIE are disabled, pin INT will remain high-impedance.
Fig 6. Interrupt scheme
Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when
TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions
when both AIE and TIE are set.
Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses
an internal clock and is dependent on the selected source clock for the countdown timer
and on the countdown value n. As a consequence, the width of the interrupt pulse varies
(see Table 7).
Table 7.
INT operation (bit TI_TP = 1)[1]
Source clock (Hz)
INT period (s)
n = 1[2]
n > 1[2]
1
1
4096
64
⁄
⁄
8192
4096
1
1
⁄
⁄
128
64
1
1
1
⁄
⁄
64
64
1
1
1
⁄
⁄
⁄
60
64
64
[1] TF and INT become active simultaneously.
[2] n = loaded countdown value. Timer stops when n = 0.
PCF8563
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
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