PCF8563
NXP Semiconductors
Real-time clock/calendar
8.3 Control registers
8.3.1 Register Control_status_1
Table 5.
Control_status_1 - control and status register 1 (address 00h) bit description
Bit
Symbol
Value
Description
Reference
7
TEST1
0[1]
normal mode
Section 8.9
must be set to logic 0 during normal operations
EXT_CLK test mode
unused
1
6
5
N
0[2]
0[1]
1
STOP
RTC source clock runs
Section 8.10
all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC
clock is stopped (CLKOUT at 32.768 kHz is still available)
4
3
N
0[2]
0
unused
TESTC
Power-On Reset (POR) override facility is disabled; set to logic 0 for
normal operation
Section 8.11.1
1[1]
000[2]
Power-On Reset (POR) override may be enabled
unused
2 to 0
N
[1] Default value.
[2] Bits labeled as N should always be written with logic 0.
8.3.2 Register Control_status_2
Table 6.
Bit
Control_status_2 - control and status register 2 (address 01h) bit description
Symbol
N
Value
000[1]
0[2]
Description
Reference
7 to 5
4
unused
TI_TP
INT is active when TF is active (subject to the status of TIE)
INT pulses active according to Table 7 (subject to the status of TIE);
Section 8.3.2.1
and
Section 8.8
1
Remark: note that if AF and AIE are active then INT will be
permanently active
3
2
AF
TF
0[2]
read: alarm flag inactive
write: alarm flag is cleared
read: alarm flag active
Section 8.3.2.1
1
0[2]
write: alarm flag remains unchanged
read: timer flag inactive
write: timer flag is cleared
read: timer flag active
1
write: timer flag remains unchanged
alarm interrupt disabled
alarm interrupt enabled
1
0
AIE
TIE
0[2]
1
0[2]
timer interrupt disabled
1
timer interrupt enabled
[1] Bits labeled as N should always be written with logic 0.
[2] Default value.
PCF8563
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Product data sheet
Rev. 10 — 3 April 2012
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