NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
4. Block diagram
PCA9555
8-bit
INPUT/
OUTPUT
PORTS
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
A0
A1
A2
write pulse
read pulse
I
2
C-BUS/SMBus
CONTROL
SCL
SDA
INPUT
FILTER
8-bit
INPUT/
OUTPUT
PORTS
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
DD
LP filter
INT
write pulse
read pulse
POWER-ON
RESET
V
DD
V
SS
002aac702
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9555
5. Pinning information
5.1 Pinning
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
002aac697
INT 1
A1 2
A2 3
IO0_0 4
IO0_1 5
IO0_2 6
IO0_3 7
IO0_4 8
IO0_5 9
IO0_6 10
IO0_7 11
V
SS
12
002aac698
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
PCA9555N
PCA9555D
IO0_6 10
IO0_7 11
V
SS
12
Fig 2.
PCA9555_8
Pin configuration for DIP24
Fig 3.
Pin configuration for SO24
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
3 of 34
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