NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
data from
shift register
configuration
register
D
FF
Q
Q1
100 kΩ
output port
register data
V
DD
data from
shift register
write
configuration
pulse
write pulse
CK
Q
D
FF
CK
Q
I/O pin
Q2
output port
register
input port
register
D
FF
Q
V
SS
input port
register data
read pulse
CK
to INT
polarity inversion
register
data from
shift register
write polarity
pulse
D
FF
CK
Q
polarity
inversion
register data
002aac703
At power-on reset, all registers return to default values.
Fig 9.
Simplified schematic of I/Os
6.5 Bus transactions
6.5.1 Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address and setting the least
significant bit to a logic 0 (see
The command byte is
sent after the address and determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are configured to operate as four register pairs.
The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration
Ports. After sending data to one register, the next data byte will be sent to the other
register in the pair (see
and
For example, if the first byte is sent to
Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, each 8-bit register may be updated independently of the other registers.
PCA9555_8
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
9 of 34
PHILIPS [ NXP SEMICONDUCTORS ]
