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Product data sheet
Rev. 08 — 22 October 2009
© NXP B.V. 2009. All rights reserved.
PCA9555_8
NXP Semiconductors
data into port 0
data into port 1
INT
t
v(INT_N)
SCL
1
2
3
4
5
6
7
8
R/W
9
I0.x
A
7
6
5
4
3
2
1
0
A
7
6
5
I1.x
4
3
2
1
0
A
7
6
5
I0.x
4
3
2
1
0
A
7
6
5
I1.x
4
3
2
STOP condition
1
0
1
P
t
rst(INT_N)
slave address
SDA S
0
1
0
0 A2 A1 A0 1
16-bit I
2
C-bus and SMBus I/O port with interrupt
START condition
read from port 0
acknowledge
from slave
acknowledge
from master
acknowledge
from master
acknowledge
from master
non acknowledge
from master
read from port 1
002aac223
PCA9555
Remark:
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read Input Port register).
12 of 34
Fig 13. Read Input port register, scenario 1
PHILIPS [ NXP SEMICONDUCTORS ]
