Philips Semiconductors
Product data
Octal SMBus and I
2
C registered interface
PCA9556
slave address
acknowledge
from slave
acknowledge
from slave
slave address
acknowledge
from slave
data from register
acknowledge
from master
S
0
0
1
1
A2 A1 A0
0
R/W
A
COMMAND BYTE
A
S
0
0
1
1
A2 A1 A0
1
R/W
A
DATA
first byte
A
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
data from register
no acknowledge
from master
DATA
last byte
NA
P
su01052
Figure 9. READ from register via Read byte protocol
slave address
data from port
data from port
SDA
S
0
0
1
1
A2
A1
A0
1
R/W
A
acknowledge
from slave
DATA 1
A
acknowledge
from master
DATA 4
NA
P
stop
condition
start condition
no acknowledge
from master
READ FROM
PORT
DATA INTO
PORT
t
ph
DATA 2
DATA 3
t
ps
DATA 4
SW00799
NOTES:
1. This figure assumes the command byte has previously been programmed with 00h.
2. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid
(output mode). Input data is lost.
Figure 10. READ input port register via Receive byte protocol
2002 Mar 28
8
PHILIPS [ NXP SEMICONDUCTORS ]
