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PCA9556PW 参数 Datasheet PDF下载

PCA9556PW图片预览
型号: PCA9556PW
PDF下载: 下载PDF文件 查看货源
内容描述: 八SMBus和I2C接口注册 [Octal SMBus and I2C registered interface]
分类和应用:
文件页数/大小: 13 页 / 98 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
Product data
Octal SMBus and I
2
C registered interface
PCA9556
REGISTERS
Command Byte
Command
0
1
2
3
Protocol
Read byte
Read/write byte
Read/write byte
Read/write byte
Function
Input port register
Output port register
Polarity inversion register
Configuration register
Register 2 — Polarity Inversion Register
bit
default
N7
1
N6
1
N5
1
N4
1
N3
0
N2
0
N1
0
N0
0
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
This register enables polarity inversion of pins defined as inputs by
register 3. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s original
polarity is retained.
Register 3 — Configuration Register
bit
default
Register 0 — Input Port Register
I7
I6
I5
I4
I3
I2
I1
I0
This register is an read-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by register 3. Writes to this register have no effect.
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
This register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output.
Register 1 — Output Port Register
bit
default
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
RESET
Power-on Reset
When power is applied to V
DD
, an internal power-on reset holds the
PCA9556 in a reset state until V
DD
has reached V
POR
. At that point,
the reset condition is released and the PCA9556 registers and
SMBus state machine will initialize to their default states.
This register reflects the outgoing logic levels of the pins defined as
outputs by register 3. Bit values in this register have no effect on
pins defined as inputs. In turn, reads from this register reflect the
value that is in the flip-flop controlling the output selection, NOT the
actual pin value.
External Reset
A reset can be accomplished by holding the RESET pin low for a
minimum of T
W
. The PCA9556 registers and SMBus/I
2
C state
machine will be held in their default state until the RESET input is
once again high. This input typically requires a pull-up to 3.3 V V
CC.
2002 Mar 28
4