Philips Semiconductors
Product data
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
P87LPC764
PIN DESCRIPTIONS
MNEMONIC
P0.0–P0.7
PIN NO.
1, 13, 14,
16–20
TYPE
I/O
NAME AND FUNCTION
Port 0:
Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches are configured in
the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined
by the PRHI bit in the UCFG1 configuration byte. The operation of port 0 pins as inputs and outputs
depends upon the port configuration selected. Each port pin is configured independently. Refer to the
section on I/O port configuration and the DC Electrical Characteristics for details.
The Keyboard Interrupt feature operates with port 0 pins.
Port 0 also provides various special functions as described below.
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
Comparator 2 output.
Comparator 2 positive input B.
Comparator 2 positive input A.
Comparator 1 positive input B.
Comparator 1 positive input A.
Comparator reference (negative) input.
Comparator 1 output.
Timer/counter 1 external count input or overflow output.
1
20
19
18
17
16
14
13
P1.0–P1.7
2–4, 8–12
O
I
I
I
I
I
O
I/O
I/O
Port 1:
Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted
below. Port 1 latches are configured in the quasi-bidirectional mode and have either ones or zeros
written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The
operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration
selected. Each of the configurable port pins are programmed independently. Refer to the section on I/O
port configuration and the DC Electrical Characteristics for details.
Port 1 also provides various special functions as described below.
P1.0
P1.1
P1.2
TxD
RxD
T0
SCL
INT0
SDA
INT1
RST
Transmitter output for the serial port.
Receiver input for the serial port.
Timer/counter 0 external count input or overflow output.
I
2
C serial clock input/output. When configured as an output, P1.2 is open
drain, in order to conform to I
2
C specifications.
External interrupt 0 input.
I
2
C serial data input/output. When configured as an output, P1.3 is open
drain, in order to conform to I
2
C specifications.
External interrupt 1 input.
External Reset input (if selected via EPROM configuration). A low on this pin
resets the microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor begins execution at address 0. When used
as a port pin, P1.5 is a Schmitt trigger input only.
12
11
10
O
I
I/O
I/O
I
I/O
I
I
9
P1.3
8
4
P1.4
P1.5
P2.0–P2.1
6, 7
I/O
Port 2:
Port 2 is a 2-bit I/O port with a user-configurable output type. Port 2 latches are configured in the
quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by
the PRHI bit in the UCFG1 configuration byte. The operation of port 2 pins as inputs and outputs
depends upon the port configuration selected. Each port pin is configured independently. Refer to the
section on I/O port configuration and the DC Electrical Characteristics for details.
Port 2 also provides various special functions as described below.
P2.0
X2
CLKOUT
Output from the oscillator amplifier (when a crystal oscillator option is
selected via the EPROM configuration).
CPU clock divided by 6 clock output when enabled via SFR bit and in
conjunction with internal RC oscillator or external clock input.
Input to the oscillator circuit and internal clock generator circuits (when
selected via the EPROM configuration).
7
O
6
V
SS
V
DD
5
15
I
I
I
P2.1
X1
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal operation as well as Idle and
Power Down modes.
2003 Sep 03
6
PHILIPS [ NXP SEMICONDUCTORS ]
