NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Contents
1
General description ............................................ 1
10.4.4
Buck regulators ................................................32
2
3
4
5
6
7
Features and benefits .........................................1
Simplified application diagram ..........................2
Applications .........................................................3
Orderable parts ................................................... 3
Internal block diagram ........................................4
Pinning information ............................................ 5
Pinning ...............................................................5
Pin definitions .................................................... 5
General product characteristics ........................ 8
Absolute maximum ratings ................................ 8
Thermal characteristics ......................................8
Power dissipation .............................................. 9
Electrical characteristics .................................. 10
General specifications ..................................... 10
Current consumption ....................................... 11
Detailed description ..........................................11
Features ...........................................................11
Functional block diagram .................................13
Functional description ......................................13
Power generation ............................................ 13
Control logic .....................................................14
Interface signals .............................................. 14
10.4.4.1 Current limit ..................................................... 33
10.4.4.2 General control ................................................ 33
10.4.4.3 SW1A/B/C ........................................................38
10.4.4.4 SW2 ................................................................. 53
10.4.4.5 SW3A/B ........................................................... 61
10.4.4.6 SW4 ................................................................. 74
7.1
7.2
8
8.1
8.2
8.3
8.4
8.4.1
8.4.2
9
9.1
9.2
9.3
9.3.1
9.3.2
9.3.2.1
10
10.4.5
Boost regulator ................................................ 82
10.4.5.1 SWBST setup and control ............................... 82
10.4.5.2 SWBST external components ..........................83
10.4.5.3 SWBST specifications ..................................... 83
10.4.6
LDO regulators description ..............................84
10.4.6.1 Transient response waveforms ........................85
10.4.6.2 Short-circuit protection .....................................85
10.4.6.3 LDO regulator control ...................................... 86
10.4.6.4 External components .......................................89
10.4.6.5 LDO specifications ...........................................90
10.4.6.6 VSNVS LDO/switch ....................................... 100
10.4.6.7 Coin cell battery backup ................................104
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.6
10.6.1
10.6.2
10.7
10.7.1
11
11.1
11.1.1
11.1.2
12
12.1
12.2
12.3
12.4
12.5
12.6
12.6.1
12.6.2
13
Control interface I2C block description .......... 105
I2C device ID .................................................105
I2C operation .................................................105
Interrupt handling ...........................................106
Interrupt bit summary .....................................106
Specific registers ........................................... 112
IC and version identification .......................... 112
Embedded memory ....................................... 113
Register bitmap ............................................. 113
Register map ................................................. 114
Typical applications ........................................122
Introduction .................................................... 122
Application diagram ....................................... 123
Bill of materials ..............................................123
PF4210 layout guidelines ............................... 127
General board recommendations .................. 127
Component placement ...................................128
General routing requirements ........................128
Parallel routing requirements .........................128
Switching regulator layout recommendations . 129
Thermal information .......................................130
Rating data .................................................... 130
Estimation of junction temperature ................ 130
Packaging ........................................................ 130
Packaging dimensions ...................................131
Revision history .............................................. 134
Legal information ............................................135
Functional
block
requirements
and
behaviors ........................................................... 15
Startup ............................................................. 15
Device startup configuration ............................ 15
One time programmability (OTP) .....................18
10.1
10.1.1
10.1.2
10.1.2.1 Startup sequence and timing ...........................18
10.1.2.2 PWRON pin configuration ............................... 19
10.1.2.3 I2C address configuration ................................19
10.1.2.4 Soft start ramp rate ......................................... 20
10.1.3
10.1.4
10.1.5
10.2
OTP prototyping .............................................. 20
Reading OTP fuses ......................................... 21
Programming OTP fuses .................................21
16 MHz and 32 kHz clocks ..............................21
Clock adjustment ............................................. 22
Bias and references block description ............. 22
Internal core voltage references ...................... 22
10.2.1
10.3
10.3.1
10.3.1.1 External components .......................................23
10.3.2 VREFDDR voltage reference ...........................23
10.3.2.1 VREFDDR control register .............................. 23
10.4
10.4.1
10.4.1.1 On mode ..........................................................26
10.4.1.2 Off mode ..........................................................26
10.4.1.3 Standby mode ................................................. 26
10.4.1.4 Sleep mode ..................................................... 27
10.4.1.5 Coin cell mode .................................................28
Power generation ............................................ 25
Modes of operation ..........................................25
13.1
14
15
10.4.2
State machine flow summary .......................... 28
10.4.2.1 Turn on events ................................................ 29
10.4.2.2 Turn off events ................................................ 30
10.4.3
Power tree ....................................................... 30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 November 2018
Document identifier: PF4210
NXP [ NXP ]
