NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
5. Block diagram
ethernet
PHY
interface
USB
transceiver
interface
LCD
panel
interface
32-bit wide
external
memory
ETHERNET
10/100
MAC
4
VFP9
ETB
ETM 9
D-CACHE
32 kB
D-SIDE
CONTROLLER
DATA
master layer
slave port
0
1
2
3
0
ARM
9EJS
I-CACHE
32 kB
I-SIDE
CONTROLLER
INSTRUCTION
1
DMA
CONTROLLER
M0
2
M1
3
5
6
USB OTG
CONTROLLER
LCD
CONTROLLER
MMU
EXTERNAL
MEMORY
CONTROLLER
port 3
port 4
port 0
5
AHB slaves
SLC
NAND
6
DMA
MLC
NAND
AHB
APB slaves
TO
APB
BRIDGE
SPI
×
2
SRAM
256 kB
ROM
16 kB
SD
CARD
SSP
×
2
I2S
×
2
USB
SDRAM
ETB
ETHERNET
LCD
register interfaces
7
32 bit, AHB matrix
AHB
APB slaves
TO
APB
BRIDGE
I2C
×
2
STANDARD
UART
×
4
MOTOR
CONTROL PWM
= Master/Slave connection supported
by the multilayer AHB matrix
WATCHDOG
TIMER
AHB
FAB slaves
TO
APB
BRIDGE
SYSTEM
CONTROL
TIMERS
×
6
PWM
×
2
RTC
GPIO
INTERRUPT
CONTROL
DEBUG
KEY
SCANNER
HS UART
×
3
UART
CONTROL
10-BIT
ADC/TS
002aae397
Fig 1.
Block diagram of LPC3220/30/40/50
LPC3220_30_40_50_1
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 February 2009
4 of 73
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