LPC2212/2214
NXP Semiconductors
16/32-bit ARM microcontrollers
• When the SPI interface is used in Master mode, the SSEL pin is not needed (can be
used for a different function).
6.13 SSP controller (LPC2212/2214/01 only)
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI1 to SSP and back.
6.13.1 Features
• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• Four to 16 bits per frame.
6.14 General purpose timers
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.14.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
• Timer or external event counter operation
• Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs per timer corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
LPC2212_2214_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 January 2008
19 of 45
NXP [ NXP ]
