NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Ordering information ..........................................2
Tab. 37. DEVSTAT1 - device status register (address
02h) bit description ..........................................33
Tab. 38. DEVSTAT2 - device status register (address
03h) bit allocation ............................................33
Tab. 39. DEVSTAT2 - device status register (address
03h) bit description ..........................................34
Tab. 40. DEVSTAT3 - device status register (address
04h) bit allocation ............................................34
Tab. 41. DEVSTAT3 - device status register (address
04h) bit description ..........................................35
Ordering options ................................................2
Pin description ...................................................4
Self-test control register .................................... 8
Self-test control bits for sense data fixed
value verification ............................................... 8
IIR low pass filter coefficients ..........................10
Temperature conversion variables .................. 13
Sensor data register read wrap-around
Tab. 6.
Tab. 7.
Tab. 8.
description ....................................................... 17
SPI command format ...................................... 19
Tab. 9.
Tab. 42. TEMPERATURE
(address 0Eh) bit allocation .............................35
Tab. 43. DEVLOCK_WR lock register writes
register (address 10h) bit allocation ................ 35
Tab. 44. DEVLOCK_WR lock register writes
- temperature register
Tab. 10. SPI command bit allocation .............................20
Tab. 11. SPI response format ....................................... 20
Tab. 12. Register read command message format ....... 21
Tab. 13. Register read command message bit field
descriptions ..................................................... 21
Tab. 14. Register read response message format ........ 21
Tab. 15. Register read response message bit field
descriptions ..................................................... 22
Tab. 16. Register write command message format ....... 22
Tab. 17. Register write command message bit field
descriptions ..................................................... 22
Tab. 18. Register write response message format ........ 23
Tab. 19. Register write response message bit field
descriptions ..................................................... 23
Tab. 20. Sensor data request command message
format .............................................................. 23
Tab. 21. Sensor data request command message bit
field descriptions ............................................. 23
Tab. 22. Sensor data request response message
format .............................................................. 24
Tab. 23. Sensor data request response message bit
field descriptions ............................................. 24
Tab. 24. Reserved command message format ..............24
Tab. 25. Reserved command message bit field
descriptions ..................................................... 24
Tab. 26. Reserved command response message
format .............................................................. 24
Tab. 27. Reserved command response message bit
field descriptions ............................................. 25
Tab. 28. SPI Command Message CRC ........................ 25
Tab. 29. SPI Response Message CRC .........................26
Tab. 30. Basic status field for responses to register
commands .......................................................26
Tab. 31. Error responses bit field descriptions .............. 26
Tab. 32. User-accessible data — sensor specific
information .......................................................28
Tab. 33. COUNT - rolling counter register (address
00h) bit allocation ............................................31
Tab. 34. DEVSTAT - device status register (address
01h) bit allocation ............................................32
Tab. 35. DEVSTAT - device status register (address
01h) bit description ..........................................32
Tab. 36. DEVSTAT1 - device status register (address
02h) bit allocation ............................................32
-
-
register (address 10h) bit description ..............36
Tab. 45. Device reset command sequence ...................36
Tab. 46. UF_REGION_W
register (address 14h) bit allocation ................ 36
Tab. 47. UF_REGION_R UF region selection
- UF region selection
-
register (address 15h) bit allocation ................ 37
Tab. 48. REGION_LOAD Bit Definitions ....................... 37
Tab. 49. REGION_ACTIVE Bit Definitions .................... 37
Tab. 50. COMMTYPE - communication type register
(address 16h) bit allocation .............................38
Tab. 51. COMMTYPE - communication type register
(address 16h) bit description ...........................38
Tab. 52. SOURCEID_0
register (address 1Ah) bit allocation ................39
Tab. 53. SOURCEID_1 source identification
register (address 1Bh) bit allocation ................39
Tab. 54. TIMING_CFG communication timing
-
source identification
-
-
register (address 22h) bit allocation ................ 39
Tab. 55. SPI_CFG Register (address 3Dh) bit
allocation ......................................................... 39
Tab. 56. DATASIZE Bit Definition ................................. 39
Tab. 57. SPI CRC Definition ......................................... 40
Tab. 58. WHO_AM_I - device identification register
(address 3Eh) bit allocation .............................40
Tab. 59. WHO_AM_I register values .............................40
Tab. 60. I2C_ADDRESS - I2C slave address register
(address 3Fh) bit allocation .............................41
Tab. 61. Self-Test Control Bits (ST_CTRL[3:0]) ............ 41
Tab. 62. DSP_CFG_U1 - DSP user configuration #1
register (address 40h) bit allocation ................ 42
Tab. 63. Low-pass filter selection bits (LPF[3:0]) ...........42
Tab. 64. User range selection bits (USER_
RANGE[1:0]) ....................................................42
Tab. 65. DSP_CFG_U4 - DSP user configuration #4
register (address 43h) bit allocation ................ 42
Tab. 66. DSP_CFG_U4 - DSP user configuration #4
register (address 43h) bit description ..............43
Tab. 67. DSP_CFG_U5 - DSP user configuration #5
register (address 44h) bit allocation ................ 43
Tab. 68. DSP_CFG_U5 - DSP user configuration #5
register (address 44h) bit description ..............43
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
69 / 72
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