NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Tab. 69. Self-test control bits ........................................ 43
Tab. 70. INT_CFG - interrupt configuration register
(address 45h) bit allocation .............................44
Tab. 71. INT_CFG - interrupt configuration register
(address 45h) bit description ...........................44
Tab. 72. P_INT_HI, P_INT_LO - interrupt window
comparator threshold registers (address 46h
Tab. 85. IC MANUFACTURER IDENTIFICATION
REGISTER (ICMFGID address C2h) bit
allocation ......................................................... 50
Tab. 86. PN0 Register (address C4h) bit allocation .......50
Tab. 87. PN1 Register (address C5h) bit allocation .......50
Tab. 88. SN0 Register (address C6h) bit allocation .......50
Tab. 89. SN1 Register (address C7h) bit allocation .......51
Tab. 90. SN2 Register (address C8h) bit allocation .......51
Tab. 91. SN3 Register (address C9h) bit allocation .......51
Tab. 92. SN4 Register (address CAh) bit allocation ...... 51
Tab. 93. ASICWFR# Register (address CBh) bit
allocation ......................................................... 51
Tab. 94. ASICWFR_X Register (address CCh) bit
allocation ......................................................... 51
Tab. 95. ASICWFR_Y Register (address CDh) bit
allocation ......................................................... 52
to 49h) bit allocation ........................................44
Tab. 73. P_CAL_ZERO
-
pressure calibration
registers (address 4Ch, 4Dh) bit allocation ......45
Tab. 74. DSP_STAT - DSP-specific status register
(address 60h) bit allocation .............................46
Tab. 75. DSP_STAT - DSP-specific status register
(address 60h) bit description ...........................46
Tab. 76. DEVSTAT_COPY - device status copy
register (address 61h) bit allocation ................ 46
Tab. 77. SNSDATA0_L, SNSDATA0_H - sensor data
#0 registers (addresses 62h, 63h) bit
Tab. 96. ASICWLOT_L Register (address D0h) bit
allocation ......................................................... 52
allocation ......................................................... 47
Tab. 78. SNSDATA1_L, SNSDATA1_H - sensor data
#1 registers (address 64h, 65h) bit allocation ...47
Tab. 79. SNSDATA0_TIMEx - time stamp register
(address 66h to 6Bh) bit allocation ..................48
Tab. 80. P_Max and P_Min registers (address 6Ch to
6Fh) bit allocation ............................................48
Tab. 97. ASICWLOT_H Register (address D1h) bit
allocation ......................................................... 52
Tab. 98. Lock and CRC Register bit definitions .............53
Tab. 99. Maximum ratings .............................................54
Tab. 100. Electrical characteristics — supply and I/O ..... 55
Tab. 101. Static characteristics ....................................... 55
Tab. 102. Dynamic characteristics .................................. 56
Tab. 103. External component recommendations for
I2C ...................................................................60
Tab. 104. External component recommendations for
SPI ...................................................................61
Tab. 105. Revision history ...............................................66
Tab. 81. FRT
-
free running timer registers
(addresses 78h to 7Dh) bit allocation ..............48
Tab. 82. Range Indication Bits (RANGE[3:0]) ............... 49
Tab. 83. IC TYPE REGISTER (ICTYPEID address
C0h) bit allocation ........................................... 49
Tab. 84. IC
MANUFACTURER
REVISION
REGISTER (ICREVID address C1h) bit
allocation ......................................................... 49
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Block diagram of FXPS7115D4 ........................ 3
Pin configuration for 16-pin HQFN ....................3
Voltage regulation and monitoring .....................5
User-controlled PABS common mode self-
test flowchart .....................................................7
ΣΔ converter block diagram ..............................8
Signal chain diagram ........................................ 9
Sinc filter response ........................................... 9
800 Hz, 4-pole, low-pass filter response ......... 10
800 Hz, 4-pole output signal delay ..................11
Fig. 16. I2C byte transmissions ....................................15
Fig. 17. I2C acknowledge and not acknowledge
transmission .................................................... 15
Fig. 18. I2C stop condition ........................................... 16
Fig. 19. I2C timing diagram ..........................................18
Fig. 20. Standard 32 Bit SPI protocol timing diagram ... 19
Fig. 21. SPI data output verification ............................. 27
Fig. 22. SPI timing diagram ..........................................27
Fig. 23. Absolute pressure accuracy as a function of
temperature ..................................................... 59
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10. 1000 Hz, 4-pole, low-pass filter response ....... 11
Fig. 11. 1000 Hz, 4-pole output signal delay ................12
Fig. 12. Temperature sensor signal chain block
diagram ............................................................13
Fig. 13. Common mode error detection signal chain
block diagram ..................................................13
Fig. 24. Absolute pressure accuracy multiplier over
life ....................................................................59
Fig. 25. I2C application diagram of FXPS7115D4 ........60
Fig. 26. SPI application diagram for FXPS7115D4 .......61
Fig. 27. Package outline HQFN (SOT1573-1) ..............62
Fig. 28. Package outline detail HQFN (SOT1573-1) .... 63
Fig. 29. Package outline note HQFN (SOT1573-1) ......64
Fig. 14. I2C bit transmissions .......................................14
Fig. 15. I2C start condition ...........................................14
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
70 / 72
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