NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Effect
Bus
Opcode Operand Cycles
Address
on CCR
Source Form
Operation
Description
[1]
Mode
V H I N Z C
Branch if Not
Equal
26 rr
3
BNE rel
Branch if (Z) = 0
– – – – – – rel
BPL rel
BRA rel
Branch if Plus
Branch Always
Branch if (N) = 0
No Test
– – – – – – rel
– – – – – – rel
2A rr
20 rr
3
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01 dd rr
03 dd rr
05 dd rr
07 dd rr
09 dd rr
0B dd rr
0D dd rr
0F dd rr
5
5
5
5
5
5
5
5
BRCLR
n,opr8a,rel
Branch if Bit n in
Memory Clear
Branch if (Mn) = 0
– – – – – Þ
BRN rel
Branch Never
Uses 3 Bus Cycles – – – – – – rel
DIR (b0)
21 rr
3
00 dd rr
02 dd rr
04 dd rr
06 dd rr
08 dd rr
0A dd rr
0C dd rr
0E dd rr
5
5
5
5
5
5
5
5
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BRSET n,opr8a, Branch if Bit n in
rel
Branch if (Mn) = 1
– – – – – Þ
Memory Set
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10 dd
12 dd
14 dd
16 dd
18 dd
1A dd
1C dd
1E dd
5
5
5
5
5
5
5
5
Set Bit n in
Memory
BSET n,opr8a
Mn ← 1
– – – – – –
PC ← (PC) +
0x0002
AD rr
5
push (PCL); SP ←
(SP) – 0x0001
Branch to
Subroutine
BSR rel
– – – – – – rel
push (PCH); SP ←
(SP) – 0x0001
PC ← (PC) + rel
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr ff
5
4
4
5
5
6
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
DIR
IMM
IMM
IX1+
IX+
Compare and
Branch if Equal
CBEQ oprx8,X+,
rel
– – – – – –
CBEQ ,X+,rel
9E61 rr
CBEQ oprx8,SP,
SP1
rel
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
75 / 183
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