NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
14.7 Auto-zero sequence
An auto-zero sequence is performed periodically on the input amplifier to cancel offset
errors. During reception of the SYNC pattern and body of the message, auto-zero
operations are synchronized to data edges of the incoming signal to avoid interfering
with normal reception. During the auto-zero sequence, the input amplifier is temporarily
disconnected from the external coil and connected to ground. The auto-zero sequence
takes roughly 64 μs. It is performed at each LFO period in carrier mode and on one over
four decoded data edges in data mode.
When the DECEN bit is cleared, the auto-zero sequence is performed at each LFO
period. During the 64 μs of the auto-zero sequence, the receiver is holding the state
"0" or "1" previously decoded. Since the LFR receiver is not active during this time, the
possible data-rate that the analog can detect is at least limited by this duration.
14.8 Data recovery
Rectified signals from the amplifier output are connected to the input of an averaging filter
and data slicer. The slicer thus compares the rectified signal with its own average value
to decode the data. When a carrier is present, the slicer output voltage rises and when
the carrier stops the slicer output voltage falls. The output of this comparator provides
a binary digital signal that indicates whether the carrier is present or not. This digital
signal is connected to the data clock recovery circuit, the SYNC detect circuit, and the
Manchester decoder circuit.
The Manchester decoder uses the digital output of the data slicer to detect the logic level
of each incoming data bit and to synchronize the decoder state machine. The LFPOL
polarity bit in the LFCTRLA register selects the expected encoding of the Manchester
data bit.
If a strong signal (above roughly 100 mV p-p differential) is entered into the LFR,
the input impedance will switch instantaneously to a lower programmed value (the
LOWQ[1:0] bits in the LFCTRLC) and be maintained during the current data packet if the
DEQEN bit is set. At the next ON time, the default high input impedance will be set again.
The strong signal detection and the automatic impedance change can be disabled by
clearing the DEQEN bit.
14.9 Data clock recovery and synchronization
Data clock recovery and synchronization takes place during the SYNC portion of an
incoming message. The preamble must be modulated Manchester data. The type
of required SYNC pattern determines the allowed preamble type depending on the
SYNC[1:0] control bits.
The design data rate is 3.906 kbps which gives a bit time equivalent to about 32 cycles of
the LF carrier frequency. In a Manchester encoded bit time, the carrier should be present
for either the first half or the second half of the bit time depending on whether the bit is a
logic zero or a logic one.
The LFRO clock source is 32 times the target data rate. The LFRO is used for decoding
data and also sequencing auto-zero operations.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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