NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
14.10 Manchester decode
When the LFPOL bit is clear, a logic one bit is defined as no LF carrier present for the
first half of the bit time; and a logic zero bit is defined as LF carrier present for the first
half of the bit time as shown in Figure 28. Another way to say this from the point of view
of the data slicer output is that a logic zero bit has a falling edge at the middle of the bit
time and a logic one bit has a rising edge at the middle of the bit time. The data slicer
threshold is dynamically adjusted to the midpoint between the carrier-present and no-
carrier levels at the summing node for the rectified output of the LF input amplifier.
Data slicer threshold
LF input
(shaded area
is LF carrier)
0.5 T
0.5 T
T
T
logic 1
logic 0
Data bit
(data slicer
output)
T = 1 bit time at the data rate (ex. 256 s at data rate of 3.906 kbps)
aaa-028021
Figure 28.ꢀManchester encoded datagram for LFPOL = 0
When the LFPOL bit is set, a logic one bit is defined as LF carrier present for the first half
of the bit time; and a logic zero bit is defined as no LF carrier present for the first half of
the bit time as shown in Figure 28.
Data slicer threshold
LF input
(shaded area
is LF carrier)
0.5 T
0.5 T
T
T
logic 0
logic 1
Data bit
(data slicer
output)
T = 1 bit time at the data rate (ex. 256 s at data rate of 3.906 kbps)
aaa-028022
Figure 29.ꢀManchester encoded datagram for LFPOL = 1
14.11 Duty-cycle for data mode
The definition of the duty-cycle for the Manchester encoded data depends on the relative
rise and fall times of the incoming LF carrier as shown in Figure 30.
60 40
40
60
1
0
aaa-028023
Figure 30.ꢀDefinition of duty-cycle of 40%
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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