NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
V
I
MR input
GND
t
W
V
I
CP input
GND
t
PHL
V
OH
Qn output
V
OL
V
M
001aac427
V
M
f
rec
V
M
(1) Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8.
Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CP) removal time
V
I
CP input
GND
t
su
t
h
V
I
Dn input
GND
V
M
t
su
t
h
V
M
V
OH
Qn output
V
OL
001aac428
V
M
(1) Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9.
Waveforms showing the data set-up and hold times for Dn inputs
74HC_HCT164_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 2 February 2010
10 of 20
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