Program and erase times and endurance cycles
M58LT256JST, M58LT256JSB
10
Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown
in Table 16. Exact erase times may change depending on the memory array condition. The
best case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is
when all the bits in the block are at ‘1’ (not pre-programmed). Usually, the system overhead
is negligible with respect to the erase time. In the M58LT256JST/B the maximum number of
program/erase cycles depends on the V voltage supply used.
PP
(1), (2)
Table 16. Program/erase times and endurance cycles
Parameter Condition
Parameter block (16 KWord)
Typical after
100 kW/E
cycles
Min
Typ
Max
Unit
0.4
1
1
3
2.5
4
s
s
Erase
Pre-programmed
Not pre-programmed
Word Program
Main Block
(64 KWord)
1.2
80
4
s
400
400
1200
µs
Single word
Buffer Program
80
µs
Program(3)
Buffer (32 words) (buffer program)
Main block (64 KWord)
Program
300
600
20
µs
ms
µs
25
25
Suspend latency
Erase
20
µs
Main blocks
100 000
100 000
cycles
cycles
s
Program/erase
cycles (per block)
Parameter blocks
Parameter block (16 KWord)
Main block (64 KWord)
Word program
0.4
1
2.5
4
Erase
s
80
400
µs
Single word
Buffer enhanced factory
program(4)
5
400
µs
Buffer program
180
150
360
300
5.8
1200
1000
µs
µs
ms
ms
s
Buffer (32
words)
Program(3)
Buffer enhanced factory program
Buffer program
Main Block
(64 KWords)
Buffer enhanced factory program
Buffer program
Bank (16
Mbits)
Buffer enhanced factory program
4.8
s
Main blocks
1000 cycles
2500 cycles
ms
Program/erase
cycles (per block)
Parameter blocks
Main blocks
2
Blank check
Parameter blocks
0.5
ms
1. TA = –25 to 85 °C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 3.6 V.
2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling
execution).
3. Excludes the time needed to execute the command sequence.
4. This is an average value on the entire device.
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