Status Register
M58LT256JST, M58LT256JSB
5
Status Register
The Status Register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the Status
Register (refer to Section 4.2 for more details). To output the contents, the Status Register is
latched and updated on the falling edge of the Chip Enable or Output Enable signals, and
can be read until Chip Enable or Output Enable returns to V . The Status Register can only
IH
be read using single asynchronous or single synchronous reads. Bus read operations from
any address within the bank always read the Status Register during program and erase
operations if no Read Array command has been issued.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset
by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the
device but must be reset by issuing a Clear Status Register command or a hardware reset.
If an error bit is set to ‘1’ the Status Register should be reset before issuing another
command.
The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to
Table 9 in conjunction with the following sections.
5.1
Program/Erase Controller status bit (SR7)
The Program/Erase Controller status bit indicates whether the Program/Erase Controller is
active or inactive in any bank.
When the Program/Erase Controller status bit is Low (set to ‘0’), the Program/Erase
Controller is active. When the bit is High (set to ‘1’), the Program/Erase Controller is inactive,
and the device is ready to process a new command.
The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses, the bit is High.
5.2
Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended in the
addressed block. When the erase suspend status bit is High (set to ‘1’), a Program/Erase
Suspend command has been issued and the memory is waiting for a Program/Erase
Resume command.
The erase suspend status bit should only be considered valid when the Program/Erase
Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the erase
suspend latency time of the Program/Erase Suspend command being issued, therefore, the
memory may still complete the operation rather than entering the suspend mode.
When a Program/Erase Resume command is issued the erase suspend status bit returns
Low.
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NUMONYX [ NUMONYX B.V ]
