M29W128GH, M29W128GL
DC and AC parameters
Figure 18. Chip Enable Controlled Program waveforms (8-bit mode)
3rd cycle
4th cycle
PA
Data Polling
PA
tAVAV
A0-A22/
A–1
555h
tAVEL
tELAX
tWLEL
tGHEL
tEHWH
W
G
tELEH
tEHEL1
E
tDVEH
tWHWH1
DQ7
D
AOh
PD
tEHDX
DQ0-DQ7
OUT
AI13334
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status Register Data Polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)).
4. See Table 27: Write AC characteristics, Write Enable Controlled, Table 28: Write AC characteristics, Chip Enable
Controlled and Table 26: Read AC characteristics for details on the timings.
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NUMONYX [ NUMONYX B.V ]
