M25PX64
Instructions
6.9
Read lock register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
lock register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the lock register is shifted out on serial data output
(DQ1), each bit being shifted out, at a maximum frequency f , during the falling edge of
C
Serial Clock (C).
The instruction sequence is shown in Figure 16.
The read lock register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any read lock register (RDLR) instruction, while an erase, program or write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
(1)
Table 9.
Bit
Lock register out
Bit name
Value
Function
b7-b2
Reserved
The write lock and lock down bits cannot be changed. Once a
‘1’ is written to the lock down bit it cannot be cleared to ‘0’,
except by a power-up.
‘1’
b1
Sector lock down
Sector write lock
The write lock and lock down bits can be changed by writing
new values to them.
‘0’
‘1’
‘0’
Write, program and erase operations in this sector will not be
executed. The memory contents will not be changed.
b0
Write, program and erase operations in this sector are
executed and will modify the sector contents.
1. Values of (b1, b0) after power-up are defined in Section 7: Power-up and power-down.
Figure 16. Read lock register (RDLR) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
MSB
3
2
1
0
DQ0
DQ1
Lock register out
High Impedance
2
7
6
5
4
3
1
0
MSB
AI13738
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NUMONYX [ NUMONYX B.V ]
