M25PX64
Instructions
Table 8.
Protection modes
Memory content
Protected area(1) Unprotected area(1)
W/VPP
signal
SRWD
Mode
bit
Write protection of
the status register
1
0
0
0
Status register is
writable (if the
WREN instruction
has set the WEL
bit)
Protected against
page program,
sector erase and
bulk erase
Ready to accept
page program and
sector erase
Software
protected
(SPM)
The values in the
SRWD, BP2, BP1
and BP0 bits can
be changed
1
0
1
instructions
Status register is
hardware write
protected
Protected against
page program,
sector erase and
bulk erase
Ready to accept
page program and
sector erase
Hardware
protected
(HPM)
1
The values in the
SRWD, BP2, BP1
and BP0 bits
instructions
cannot be changed
1. As defined by the values in the block protect (BP2, BP1, BP0) bits of the status register, as shown in
Table 3.
The protection features of the device are summarized in Table 8.
When the status register write disable (SRWD) bit of the status register is 0 (its initial
delivery state), it is possible to write to the status register provided that the write enable latch
(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the
whether Write Protect (W/V ) is driven High or Low.
PP
When the status register write disable (SRWD) bit of the status register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W/V ):
PP
■
If Write Protect (W/V ) is driven High, it is possible to write to the status register
PP
provided that the write enable latch (WEL) bit has previously been set by a write enable
(WREN) instruction.
■
If write protect (W/V ) is driven Low, it is not possible to write to the status register
PP
even if the write enable latch (WEL) bit has previously been set by a write enable
(WREN) instruction (attempts to write to the status register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the block protect (BP2, BP1, BP0) bits of the status
register, are also hardware protected against data modification.
Regardless of the order of the two events, the hardware protected mode (HPM) can be
entered:
■
by setting the status register write disable (SRWD) bit after driving Write Protect
(W/V ) Low
PP
■
or by driving Write Protect (W/V ) Low after setting the status register write disable
PP
(SRWD) bit.
The only way to exit the hardware protected mode (HPM) once entered is to pull Write
Protect (W/V ) High.
PP
If Write Protect (W/V ) is permanently tied High, the hardware protected mode (HPM) can
PP
never be activated, and only the software protected mode (SPM), using the block protect
(BP2, BP1, BP0) bits of the status register, can be used.
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NUMONYX [ NUMONYX B.V ]
