M25PX64
Description
Figure 1.
Logic diagram
V
CC
DQ0
C
DQ1
M25PX64
S
W/V
PP
HOLD
V
SS
AI14228b
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
I/O(1)
I/O(2)
Input
Input
Input
–
DQ0
DQ1
S
Serial Data input
Serial Data output
Chip Select
W/VPP
HOLD
VCC
VSS
Write Protect/Enhanced Program supply voltage
Hold
Supply voltage
Ground
–
1. Serves as an output during dual output fast read (DOFR) instructions.
2. Serves as an input during dual input fast program (DIFP) instructions.
Figure 2.
VDFPN8 connections
M25PX64
S
1
2
3
4
8
7
6
5
V
CC
HOLD
DQ1
W/V
C
PP
V
DQ0
SS
AI13720c
1. There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally, to
SS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
V
2. See Package mechanical section for package dimensions, and how to identify pin-1.
7/66
NUMONYX [ NUMONYX B.V ]
