M25PX64
Operating features
4.7
Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
4.7.1
Protocol-related protections
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25PX64 features the following data protection mechanisms:
Power on reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification
Program, erase and write status register instructions are checked that they consist of a
number of clock pulses that is a multiple of eight, before they are accepted for
execution
All instructions that modify data must be preceded by a write enable (WREN)
instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
–
–
–
Power-up
Write disable (WRDI) instruction completion
Write status register (WRSR) instruction completion
Write to lock register (WRLR) instruction completion
Program OTP (POTP) instruction completion
Page program (PP) instruction completion
Dual input fast program (DIFP) instruction completion
Subsector erase (SSE) instruction completion
Sector erase (SE) instruction completion
Bulk erase (BE) instruction completion
In addition to the low power consumption feature, the deep power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.
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