Instructions
M25PE80
(1)
Table 9.
Protection modes (T9HX process only )
Memory content
Protected area(2) Unprotected area(2)
W
SRW
Write protection of the
status register
Mode
signal D bit
1
0
0
0
Status register is writable
(if the WREN instruction
has set the WEL bit)
Second
software
protected
(SPM2)
Protected against
page program,
sector erase and
bulk erase
Ready to accept
page program and
sector erase
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
instructions
1
1
Status register is hardware
write protected
Protected against
page program,
sector erase and
bulk erase
Ready to accept
page program and
sector erase
Hardware
protected
(HPM)
0
1
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
instructions
1. See Important note on page 6.
2. As defined by the values in the block protect (BP2, BP1, BP0) bits of the status register, as shown in
Table 4.
The protection features of the device are summarized in Table 9.
When the status register write disable (SRWD) bit of the status register is 0 (its initial
delivery state), it is possible to write to the status register provided that the write enable latch
(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the
whether Write Protect (W) is driven High or Low.
When the status register write disable (SRWD) bit of the status register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
■
If write protect (W) is driven High, it is possible to write to the status register provided
that the write enable latch (WEL) bit has previously been set by a write enable (WREN)
instruction.
■
If write protect (W) is driven Low, it is not possible to write to the status register even if
the write enable latch (WEL) bit has previously been set by a write enable (WREN)
instruction. Attempts to write to the status register are rejected, and are not accepted
for execution. As a consequence, all the data bytes in the memory area that are
software protected (SPM2) by the block protect (BP2, BP1, BP0) bits of the status
register, are also hardware protected against data modification.
Regardless of the order of the two events, the hardware protected mode (HPM) can be
entered:
■
by setting the status register write disable (SRWD) bit after driving write protect (W)
Low
■
or by driving write protect (W) Low after setting the status register write disable
(SRWD) bit.
The only way to exit the hardware protected mode (HPM) once entered is to pull write
protect (W) High.
If write protect (W) is permanently tied High, the hardware protected mode (HPM) can never
be activated, and only the software protected mode (SPM2), using the block protect (BP2,
BP1, BP0) bits of the status register, can be used.
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NUMONYX [ NUMONYX B.V ]
