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M25P10-AVMN6TP/Y 参数 Datasheet PDF下载

M25P10-AVMN6TP/Y图片预览
型号: M25P10-AVMN6TP/Y
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位,串行闪存, 50MHz的SPI总线接口 [1 Mbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 51 页 / 989 K
品牌: NUMONYX [ NUMONYX B.V ]
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Revision history  
Table 25. Document revision history (continued)  
M25P10-A  
Date  
Revision  
Changes  
t
RES1 and tRES2 parameter timings changed for devices produced with the  
“X” process technology in Table 18 and Table 19.  
05-Jun-2006  
7
SO8 narrow package specifications updated (see Figure 26 and  
Table 21).  
Changed the minimum value for supply voltage.  
Added TLEAD and changed maximum value for VIO in Table 9: Absolute  
maximum ratings.  
Updated Section 3: SPI modes and modified Figure 3: Bus master and  
memory devices on the SPI bus.  
06-Jul-2007  
8
Note 1 to Table 13: Capacitance changed.  
Note 2 below Table 16: Instruction times (device grade 6) added.  
Changed test condition for ICC3 in Table 14 and fR in Table 20.  
Removed “low voltage” from the title. Small text changes.  
Typical values for Sector Erase and Bulk Erase modified.  
UFDFPN8 package (MLP8) added.  
Added the reference to a new process technology (code “Y”).  
Added notes below Table 10: Operating conditions, Table 15: DC  
characteristics (device grade 3), and Table 17: Instruction times (device  
grade 3).  
23-Aug-2007  
9
/Y process added to Table 24: Ordering information scheme.  
Code of the UFDFPN8 package modified.  
Small text changes.  
18-Oct-2007  
10-Dec-2007  
10  
11  
Applied Numonyx branding.  
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