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M24512-DFMC6TG 参数 Datasheet PDF下载

M24512-DFMC6TG图片预览
型号: M24512-DFMC6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位,低电压,串行闪存与54 MHz的SPI总线接口 [128-Mbit, low-voltage, serial flash memory with 54-MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 47 页 / 905 K
品牌: NUMONYX [ NUMONYX B.V ]
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Revision history  
M25P128  
13  
Revision history  
Table 21. Document revision history  
Date  
Revision  
Changes  
02-May-2005  
0.1  
First issue.  
Table 2: Protected area sizes updated.  
09-Jun-2005  
0.2  
Memory capacity modified in Section 6.3: Read identification (RDID).  
Updated tPP values in Table 17: AC characteristics for 130 nm  
devices and tVSL value in Table 8: Power-up timing and VWI  
threshold for 65 nm devices. Modified information in Section 4.1:  
Page programming and Section 6.8: Page program (PP).  
28-Aug-2005  
0.3  
Document status promoted from Target specification to Preliminary  
data.  
Packages are ECOPACK® compliant. Blank option removed under  
Plating technology in Table 20. Read Electronic Signature (RES)  
instruction removed. ICC1 parameter updated in Table 14: DC  
characteristics for 65 nm devices.  
20-Jan-2006  
1
Document status promoted from Preliminary Data to full Datasheet.  
Write Protect pin (W) changed to Write protect/enhanced program  
supply voltage (W/VPP). Section 4.4: Fast program/erase mode and  
Figure 24: VPPH timing added. Power-up specified for Fast  
Program/Erase mode in Power-up and power-down section.  
17-Oct-2006  
2
Figure 4: Bus master and memory devices on the SPI bus modified  
and Note 2 added.  
Note 1 added below Table 18: VDFPN8 (MLP8), 8-lead Very thin  
Dual Flat Package No lead, 8 × 6mm, package mechanical data.  
VIO max modified in Table 10: Absolute maximum ratings.  
10-Dec-2007  
26-Nov-2009  
3
4
Applied Numonyx branding.  
Removed references to multilevel cell technology and ECOPACK®  
packages.  
Added: Table 14: DC characteristics for 65 nm devices and Table 15:  
AC characteristics for 65 nm devices, and references to 65 nm  
process technology throughout the document  
Modified D2 value in Table 18: VDFPN8 (MLP8), 8-lead Very thin  
Dual Flat Package No lead, 8 × 6mm, package mechanical data.  
17-Dec-2009  
1-Feb-2010  
5
6
Added “Process Technology” to Ordering Information table.  
Added sector erase cycle times to Table 15.: AC characteristics for  
65 nm devices.  
Changed Icc3 test conditions in Table 14.: DC characteristics for  
65 nm devices as follows: 50 MHz to 54 MHz and 20 MHz to 33 MHz.  
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