P30
10.3
Read Configuration Register
The Read Configuration Register (RCR) is used to select the read mode (synchronous or
asynchronous), and it defines the synchronous burst characteristics of the device. To
modify RCR settings, use the Configure Read Configuration Register command (see
Section 9.2, “Device Commands” on page 45).
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 14.2, “Read Device Identifier” on page 70).
The RCR is shown in Table 25. The following sections describe each RCR bit.
Table 25: Read Configuration Register Description
Read Configuration Register (RCR)
Data
Hold
WAIT
Delay
Burst
Wrap
Read
Mode
WAIT
Polarity
Burst
Seq
CLK
Edge
RES
Latency Count
LC[2:0]
RES
RES
Burst Length
RM
15
Bit
R
WP
10
DH
9
WD
8
BS
7
CE
6
R
5
R
4
BW
3
BL[2:0]
1
14
13
12
11
2
0
Name
Description
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
15
Read Mode (RM)
Reserved (R)
14
Reserved bits should be cleared (0)
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
Latency Count (LC[2:0])
13:11
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
Wait Polarity (WP)
Data Hold (DH)
10
9
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
8
Wait Delay (WD)
Burst Sequence (BS)
0 =Reserved
1 =Linear (default)
7
Clock Edge (CE)
0 = Falling edge
1 = Rising edge (default)
6
5:4
3
Reserved (R)
Reserved bits should be cleared (0)
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
2:0
Burst Length (BL[2:0])
(Other bit settings are reserved)
Note: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0).
Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1)
combination is not supported. Table 25, “Read Configuration Register Description” on page 49 is
shown using the QUAD+ package. For EASY BGA and TSOP packages, the table reference should be adjusted using
address bits A[16:1].
November 2007
Order Number: 306666-11
Datasheet
49
NUMONYX [ NUMONYX B.V ]
