Intel® Embedded Flash Memory (J3 v. D)
Table 14.
Reset Specifications
#
Symbol
tPLPH
tPHRH
Parameter
Min
Max
Unit
Notes
RP# Pulse Low Time
P1
25
µs
1,2
(If RP# is tied to VCC, this specification is not applicable)
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration
P2
P3
100
ns
1,3
60
µs
µs
Vcc Power Valid to RP# de-assertion (high) 130nm
Vcc Power Valid to RP# de-assertion (high) 65nm
tVCCPH
300
Notes:
1.
2.
These specifications are valid for all product versions (packages and speeds).
If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
valid.
3.
7.4
AC Test Conditions
Figure 15.
AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
0.0
Test Points
VCCQ/2 Output
Note: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Figure 16.
Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Note: CL Includes Jig Capacitance
Figure 17.
Test Configuration
Test Configuration
CL (pF)
VCCQ = VCCQMIN
30
Datasheet
30
December 2007
Document Number: 316577-006
NUMONYX [ NUMONYX B.V ]
