Intel® Embedded Flash Memory (J3 v. D)
7.0
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention
Figure 7.
Timing Signal Naming Convention
E L Q V
t
Source Signal
Source State
Target State
Target Signal
Figure 8.
Timing Signal Name Decoder
Signal
Code
State
Code
Address
A
Q
D
E
High
H
L
Data - Read
Low
Data - Write
High-Z
Low-Z
Valid
Z
X
V
I
Chip Enable (CE)
Output Enable (OE#)
Write Enable (WE#)
Address Valid (ADV#)
Reset (RP#)
G
W
V
P
Invalid
Clock (CLK)
C
T
WAIT
Note:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that
refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV
(whichever is satisfied last) of the flash device. tAPA is specified in the flash device’s
data sheet, and is the address-to-data delay for subsequent page-mode reads.
December 2007
Document Number: 316577-006
Datasheet
23
NUMONYX [ NUMONYX B.V ]
