Intel® Embedded Flash Memory (J3 v. D)
4.2
56-Lead TSOP Package Pinout, 32-, 64-,128-, 256-Mbit
Figure 6.
56-Lead TSOP Package Pinout (32/64/128/256 Mbit)
A
24
A22
CE
A211
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WE#
OE#
STS
DQ
DQ
DQ
DQ
GND
DQ
DQ
DQ
DQ
VCCQ
GND
DQ
DQ
DQ
DQ
VCC
DQ
DQ
DQ
DQ
A
BYTE#
A
CE
15
7
14
Intel® Embedded Flash Memory
(28FXXXJ3D)
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
13
5
12
56-Lead TSOP
Standard Pinout
14 mm x 20 mm
Top View
4
CE
0
VPEN
RP#
A11
11
3
A10
10
A
2
9
32/64/128/256 Mbit
A
8
GND
9
A
1
7
A
8
6
A
0
5
A
0
4
A
3
A
23
2
A
2
1
Notes:
1.
2.
3.
A22 exists on 64- and 128- densities. On 32-Mbit density this signal is a no-connect (NC).
A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC)
A24 exists on 256-Mbit densities and on the other densities this signal is a no-connect (NC).
4.3
Signal Descriptions
Table 3 lists the active signals used on Intel® Embedded Flash Memory (J3 v. D) and
provides a description of each.
Table 3.
Signal Descriptions for Intel® Embedded Flash Memory (J3 v. D) (Sheet 1 of 2)
Symbol
Type
Name and Function
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This
address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
A0
Input
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
32-Mbit — A[21:1]
64-Mbit— A[22:1]
128-Mbit — A[23:1]
256-Mbit — A[24:1]
A[MAX:1]
D[7:0]
Input
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands
during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data
is internally latched during write operations.
Input/
Output
Datasheet
16
December 2007
Document Number: 316577-006
NUMONYX [ NUMONYX B.V ]
