28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
10.1.2
10.1.3
Output Disable
When OE# is at a logic-high level (V ), the flash memory device outputs are disabled. Output pins
are placed in a high-impedance state.
IH
Standby
Deselecting the flash memory device by bringing CE# to a logic-high level (V ) places the device
IH
in standby mode. Standby mode substantially reduces device power consumption, without any
latency for subsequent read accesses. In standby mode, outputs are placed in a high-impedance
state independent of OE#. If deselected during Program or Erase operation, the flash memory
device continues to consume active power until the Program or Erase operation is complete.
10.1.4
Deep Power-Down / Reset
From read mode, RP# at V for time t
does the following:
IL
PLPH
• Deselects the flash memory.
• Places output drivers in a high-impedance state.
• Turns off all internal circuits.
• After a return from reset, a time t
is required until the initial read-access outputs are valid.
PHQV
• After a return from reset, a delay (t
or t
) is required before a write can be initiated.
PHEL
PHWL
After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, and
the Status Register is set to 80H. Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
page 48 (A) illustrates this case.
If RP# is taken low for time t
during a Program or Erase operation, the operation aborts. The
PLPH
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data might be partially erased or written.
The abort process uses the following sequence:
1. When RP# goes low, the flash memory device shuts down the operation in progress, a process
that takes time t
to complete.
PLRH
2. After this time t
, the flash memory device either resets to read-array mode (if RP# has
PLRH
gone high during t
, see Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
PLRH
page 48 (B)), or enters reset mode (if RP# is still logic low after t
Power-Down/Reset Operations Waveforms” on page 48 (C)).
, see Figure 14 “Deep
PLRH
3. In both cases, after returning from an aborted operation, the relevant time t
or t
/
PHWL
PHQV
t
must elapse before initiating a Read or Write operation, as discussed in the previous
PHEL
paragraph. However, in this case, these delays are referenced to the end of t
when RP# goes high.
rather than
PLRH
As with any automated device, RP# must be asserted during system reset. When the system
finishes reset, the processor expects to read from the flash memory. Automated flash memories
provide status information when read during program or Block-Erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization cannot occur, because the flash
memory might be providing status information instead of array data.
Intel® Flash memories allow proper CPU initialization after a system reset, using the RP# input. In
this application, RP# is controlled by the same RESET# signal that resets the system CPU.
18 Aug 2005
52
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
NUMONYX [ NUMONYX B.V ]
